The present disclosure relates to electronic circuits, and more specifically, to improving the layout of control clock trees in hierarchical circuit designs.
Very large scale integrated circuit (VLSI) designs can incorporate high speed circuits that execute functions at clock rates of several billions of cycles per second. The functions executed by these circuits are often partitioned into several stages, forming a pipeline to improve speed and overall performance. In a hierarchical VLSI design, the function partitions can be allocated to disparate hierarchical sub-units or cells to, for example, reduce design time and improve testing efficiency. To enable these disparate partitions to perform an integrated function, centrally generated control clock signals can be used to synchronize the generation of outputs from a given stage of the integrated with the consumption of inputs by another stage. Synchronization within individual partitions is also necessary. One method of addressing the synchronization problem is to distribute control clock signals across a design using a staging clock tree having multiple levels of staging latches (e.g., a staging tree). The staging latches then distribute the clock control signals to within a given sub-unit and between multiple sub-units.